SiC MOSFETs enables fast switching that results in the development of a high dVDS/dt across the device. Further, the value of dVDS/dt is affected by various parameters which change during operation of a power converter. Hence gate driver resistance selection process to limit dVDS/dt to a desired value, must include the impact of all the operating parameters in the selection process. However, such a methodology incorporating the impact of all key parameters i.e.: (i) device current (IDS), (ii) junction temperature (TJ ), and (iii) drain to source (VDS) blocking voltage, has not been reported in the literature. This manuscript first presents an analysis on the impact of these three parameters on dVDS/dt. Furthermore, this manuscript considers devices from different manufacturers and investigates the variation in their impact on dVDS/dt due to operational parameter variation. Next, it presents a scheme for gate driver resistance selection based on the aforementioned analysis. Finally, experimental results are included (i) to validate the analysis, (ii) to show the device-dependent variation in the impact on dVDS/dt, and (iii) to validate the proposed gate resistance selection scheme.
