T04.9 - SiC Engineered Substrate: Increasing SiC MOSFETs Current Density from Device to Module Level

The layer transfer technology enables the integration of a very high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer to lower device conduction and switching losses. With this new engineered semiconductor substrate, Schottky barrier vertical structures were prepared for power cycling tests (PCT) measurements. The devices' thermal resistance, RTH, remained within the specifications of AQG324 for more than 250k cycles for samples prepared from SiC engineered substrates. In addition to a higher current rating (up to 20%) and a simplification of the device fabrication process, SiC engineered substrates bring a more reliable SiC die attach within the power module with a doubled lifetime for a delta T of 120K with silver sintering die attach.