IS16.1 - Increasing SiC Power Devices Current Density up to 30% Through 150 & 200mm Semiconductor Substrate Engineering

The Smart Cut™ technology enables the integration of very high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (below 5mOhm.cm) to lower device conduction and switching losses both for 150mm and 200mm wafer diameter. Based on material characterisation, we anticipate a benefit of up to 15% in terms of RDSon for state of the art 1200V SiC MOSFET. 1200V SiC MPS diodes and SiC MOSFETs have been fabricated by Fraunhofer IISB. Forward voltage drop reduction has been validated on Schottky contacts. Full MPS and MOSFET static performances will be presented. In addition to this benefit, material characterization is demonstrating an improved resilience with regards to bipolar degradation.