The small overvoltage margin is a critical concern for the gate reliability and driver design of enhancement-mode (E-mode) p-gate GaN high electron mobility transistors (HEMTs). This work evaluates the gate overvoltage robustness of an industrial p-gate GaN HEMT with a monolithic IC interface designed to prevent the device’s false turn-on under high dv/dt and withstand the overvoltage in the driving loop. A circuit testbed is developed to produce resonant voltage overshoot in the gate loop for characterizing the dynamic gate breakdown voltage (BVG,DYN). Such tests are performed at different bias conditions of the IC, at two temperatures (25 oC and 150 oC), and under two drain-source conditions, i.e., the drain-source-grounded (DSG) and inductive hard switching (HSW) conditions. The GaN HEMT with the smart IC interface shows a BVG,DYN up to 84 V, which is much higher than that of the standalone GaN HEMT (30 V) as well as the Si IGBT and SiC MOSFET tested under the same setup. These results show great potential of the monolithic GaN IC to enhance the GaN HEMT gate robustness.
