The rapid growth of the electric vehicle (EV) market has led to increased demand for advanced semiconductor technologies, such as Gallium Nitride (GaN) and Silicon Carbide (SiC) , to enhance the efficiency and performance of EV traction inverters and on-board chargers. Multiple power MOSFETs are integrated into power modules. As a result, the need for wafer-level burn-in to screen for bare known-good-die (KGD) has grown. Semiconductor wafer-level burn-in test equipment manufacturers face unique challenges in high voltage, with the thousands of volts required for burn-in testing and requiring contact to the full wafer and 100% of the die to deliver a viable technical solution which meets the cost requirements of a MOSFET. This abstract presents an overview of the key challenges encountered in this domain, die isolation, including preventing voltage arcing across the wafer due to tight geometries, ensuring effective contact with all die on the wafer, and not impacting neighboring dies by the creation of addition failures beyond the actual failing die.
