Following the top-rated 2022 APEC seminar on PCB layout, this fully updated seminar covers additional topologies, and focuses more on the process of understanding where transient currents flow, and how to best route them for a wide variety of topologies and applications.
GaN transistors have an extremely high gain-bandwidth product, which can make circuit layout and routing more challenging than any other transistor technology. Whether you plan to use discrete GaN transistors with external gate drivers, or package-integrated driver+transistor, these layout and routing fundamentals apply just the same. The only difference is that the layout and routing inside the package is pre-defined for integrated GaN.
Understanding and using these techniques will help you to minimize ringing and overshoot on the Bus and gate signals, and achieve cleaner, lower-noise switching. In addition, low loop-inductance generally reduces radiated EM fields, helping to improve on-board EMC issues as well as lower conducted and radiated emissions.
The main focus of this seminar is on transistors in the 650 V class, at power levels from 50 W to 20 kW. The intended audience is students and practicing power engineers working with GaN transistors.
