This paper presents a thermal modeling technique for 650 V / 7.5 A GaN HEMTs under accelerated thermal cycling (ATC) tests. The thermal modeling addresses the limitations caused by the slow response of the sensors used for monitoring the junction temperatures (Tj) of GaN HEMT devices under test (DUTs) over wide thermal cycling test windows. Experimental investigations of several GaN HEMTs under different ATC windows aid in the thermal analysis and modeling of the hardware testing setup. Extensive analysis, including the DUTs and sensing components, is carried out using the Foster thermal model, and a graphical extrapolation method to estimate the system's thermal time constant. Preliminary modeling of the same system is developed in Ansys SIwave for further validation and explanation of the system’s thermal performance. The results reveal that the thermal time constant of sensing the Tj using a thermistor attached near the DUT is around 4 s – which can expose the GaN DUT to thermal runaway as the DUT’s on-state resistance increases rapidly at high temperatures (>125 °C).
