This work presents a thorough investigation on new dynamic stress tests that are nowadays required to demonstrate SiC MOSFET reliability. A dedicated setup is built to compare long term degradation in Gate Switching Stress (GSS) and Application Switching Stress (ASS), the latter based on a synchronous boost converter. As a main finding of the study, it is experimentally observed that ASS may induce a substantially larger degradation of the threshold voltage (Vth) compared to GSS. In fact, even with identical driving conditions, ASS test enhances the maximum turn-on dvGS/dt before the Miller plateau in both high-side and low-side SiC MOSFETs. Moreover, a physical explanation based on unequal parasitic capacitances between GSS and ASS is provided by means of TCAD finite-element simulations. These results oppose previously reported experiments and imply the need to revisit the definition of GSS test to predict SiC MOSFET degradation in some applications.
