Converters with high power density are becoming a necessity in applications such as traction inverters, and electric vehicles, where power in the range of a few hundreds of kilo-watts is required to be processed by the inverter stage. As the inverters are often hard-switched, SiC power modules can enable high power density due to their superior switching loss, conduction loss, and thermal performance. However, due to fast switching transients of SiC MOSFETs, circuit parasitics can significantly impact the switching dynamics resulting in prolonged oscillation, high device stress, and crosstalk and EMI-related issues. Moreover, when the internal geometry of SiC modules is unknown, measurement becomes the sole option to estimate these parasitics, which is also important for the optimal design of the power converter. In this paper, a systematic approach of estimating parasitic inductances of a 200~kW SiC-based stack is presented. The accuracy of this proposed method is verified through experiment and electromagnetic simulation with the help of Ansys Q3D Extractor.
