In order to conduct proper reliability investigations on power electronic systems, Silicon Carbide (SiC) MOSFETs need aging models to predict the degradation of electrical parameters for longterm operation under random mission profiles. Gate Switching Instability (GSI) has been recently pinpointed as a dominant mechanism for evaluating the threshold voltage and on-state resistance degradation. This work proposes a new approach to describe the threshold voltage drift of SiC MOSFETs due to GSI by means of a compact computational model. A novel methodology is proposed to calibrate this computational aging model using experimental data, along with its extrapolation to a generic set of usage conditions. To our knowledge, this is the first time that a GSI degradation model is proposed with explicit dependencies on driving conditions like low/high driver voltage and gate resistor.
