A bridgeless flyback power factor correction rectifier is implemented to reduce common-mode (CM) noise. The high-frequency equivalent circuit with parasitic capacitances is analyzed to suggest design guidelines of the printed circuit board layout and transformer winding. The design method achieves the balance conditions in the equivalent circuit which suppresses the CM noise without additional inductors or capacitors. Experimental results by a 115 VAC-48 V, 72-W prototype bridgeless flyback rectifier demonstrate a reduction in CM noise by maximum 30 dBμV at the frequency range of 150 kHz-30 MHz. To verify that the implementation by the proposed design method is optimal, capacitors of a few tens of picofarad were intentionally added and then the CM noise increased back.
