D07.20 - Common-Mode Voltage in Three-Level T-Type Inverter: Modeling, Analysis, and Compensation

This paper investigates the origins of common-mode voltage (CMV) noises in SiC MOSFET-based three-level T-type inverters (3LT2Is), targeting adjustable speed drive (ASD) systems, and proposes methods for their mitigation. Achieving zero CMV (ZCMV) is theoretically unattainable in a two-level voltage source inverter (2L-VSI), but a 3LT2I with specific switching states offers a feasible solution. Nevertheless, ZCMV methods leads to significant CMV noise due to differences in output voltage transition times and the dead-time (DT) effect. The work proposes a method to mitigate these CMV noises through precisely adjusting the transition timing of gate drive signals. This method can minimize passive filter size and reduce electromagnetic interference (EMI) associated with CMV.