Active gate drivers for wide-bandgap devices are designed to reduce current overshoot and parasitic ringing caused by high dv/dt and di/dt transients while at the same time enabling high switching speeds. This work presents a 3-Level Active Gate Driver (3L-AGD) network which reacts to changes of the gate-source voltage without a µC or an FPGA controlling active components. The proposed system can be operated under a variety of operating conditions, such as different load voltages or load currents. Optimal operating conditions for the 3L-AGD are developed to minimize current peaks and energy losses. In the double-pulse test, the operating principle of the 3L-AGD can be confirmed, and the reduced energy losses are determined to be 10-20% less and with equal or lower current overshoots compared to a conventional gate driver.
