In this paper, a three-level buck converter topology is proposed for use as a USB 3.1 charger (48V input, 240W output power). The performance of the circuit is simulated by incorporating estimated parasitic inductances based on the layout of the designed 4 level PCB. The impact of varying loop inductances is considered. Experimental waveforms and efficiency measurements are recorded and analysed. Later, the layout is further optimized by moving from a lateral power loop to a vertical power loop. This paper will illustrate the importance of considerations such as loop inductance and circuit parasitics, and go over the next iteration of the PCB that makes use of a vertical loop in order to further minimize loop inductance and optimize the power converter’s performance.
