With the design of current and next generation performance AI/xPU products in the latest FinFET processes, companies are challenged by the increased power consumption and proliferation of voltage rails in the development of their package and PCB voltage regulators and power distribution network (PDN) designs. In particular, difficulties with transients, network parasitics and even rail/ball count requirements are forcing products to be run in less than optimal conditions due to the power delivery bottleneck. In this paper, we will look at emerging technologies allowing this conversion to happen inside the product package, reducing parasitics, ball count and PCB rail count requirements.
.jpg "Trey A. Roessig, PhD (he/him/his) photo")