This presentation will provide an overview of the causes of switch node negative transients in high voltage half-bridge designs, and a review of the designs and topologies that are more susceptible to it. We will then deep-dive into the effects of these transients from a gate driver perspective, and recommendations for both prevention and mitigation. We’ll close with techniques for testing the gate driver’s negative transient robustness in a controlled setup.
.jpg "Pankaj Pandey, Masters in Circuit Design (he/him/his) photo")