IS13.6 - The Challenges of 12V Input for Dual Entry Power Design and the Future of 48V HVDC in Data Center

Wednesday, February 28, 2024

4:05 PM – 4:30 PM PST

Location: Grand Ballroom B

Industry Session Presenter(s)

Patt Chang, MA

Senior Staff Engineer
Intel

Presentation
Chi Hsu, MA (he/him/his)

Senior Power Design Engineer
Google LLC

Presentation
Shuai Jiang, PhD

Sr Staff Power Engineer
Google LLC
ZY

Zichao Ye

PhD student
University of California, Berkeley

This presentation is intended to address the challenges using conventional 12V input for processor power design from the impacts of power loss, signal integrity, thermal and hence to pursue 48V HVDC design on mother board. It also describes emerging power architectures in data center.