The aim of this topic is to analyze in a deep way the factors having impact on the “Cross-conduction” also known as “Parasitic Turn-On”, that can happen during switching transients of power converters. As it is known, Parasitic Turn-on takes place when one device is turning on and the complementary one, that is in off state with negative gate-source voltage, is triggered in uncontrolled way due to induced gate-source voltage through Miller capacitance, hence the load current conduction will be affected by the body diode of the triggered passive device, which is in reverse recovery and also by its channel. A two-level SiC MOSFETs based half-bridge converter topology is used to perform experimental tests, to highlight the main parameters which have significant impact on power converter losses; among these, parasitic capacitances, that define the Miller ratio, are the most significant and it will be shown how their manipulation can change Parasitic Turn-on and SiC MOSFET transient behavior.
